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Si3460-EVB
6. Design and Layout Considerations
6.1. General Recommendations
The Si3460-EVB schematic and layout are intended to be used as a reference for all customer designs. The
Si3460-EVB has been tested by the University of New Hampshire Interoperability Lab (UNH IoL) to comply with the
relevant IEEE 802.3 Clause 33 specifications. UNH test reports can be downloaded from www.silabs.com/PoE.
Since the Si3460’s performance in an application depends on external components and PCB layout, customers are
ultimately responsible for validating their design’s conformance to all relevant industry, safety, and
customer-specific requirements. For applications support, contact PoEinfo@silabs.com.
6.2. Isolation
The IEEE 802.3 specification requires the PSE output power to be isolated from earth ground*. To accomplish this,
the input power source must be isolated from earth ground. Also, do not connect the Si3460's ground connection
(pin #11) to earth ground, as this pin serves a circuit reference point only in the Si3460-EVB.
*Note: If the input power supply is referenced to earth ground, and if one of the output pads is connected to ground, it can
create a high-current fault condition that will not be protected.
6.3. SELV-Compliant Output Voltage
Since the output of the Si3460-EVB reference design is designed to be less than 57 Vdc under all conditions, it is
considered a SELV circuit.
The Si3460-EVB is designed to produce a negative output voltage with respect to the input voltage. The reason
this is done is because the Si3460 will often be used in applications and environments where a standard telephone
circuit or SLIC, such as the Si3210/15/32/33, will be powered from the same 12 to 15 V isolated input power
supply. Conventionally, these circuits produce large negative operating voltages. Since the Si3460-EVB reference
design is also designed to produce negative voltages, the Si3460-EVB implementation eliminates the possibility of
a hazardous voltage difference between a SLIC output and the Si3460-EVB's PSE output.
6.4. Surge Protection
The SI3460-EVB applications design includes a clamp diode, D12, to protect against the 50 μs intra-building
lightening surges, as specified in IEEE 802.3. Additional protection, such as a 1 A fuse in the output circuit, may be
required for applications in which the Ethernet cabling is not intra-building.
6.5. EMI and EMC
The SI3460-EVB applications solution is designed to be compliant with FCC Class B (CISPR22) for radiated
emissions, as well as FCC Part 15 (EN55022) for conducted emissions. The PCB layout of the Si3460-EVB should
be closely followed to prevent EMI and EMC issues.
The keys to robust EMI and EMC performance are:
?? Keep
the current loops in the switcher circuit small-diameter.
?? Lay out the current loop when the FET is on similarly to the current loop when the FET is off.
?? Connect filter caps to the power circuitry and not to reference planes.
?? For better EMI performance, use shielded inductors for L1 and L4.
6.6. Thermal Considerations
Inductor L1: For improved thermal performance, Silicon Laboratories strongly recommends using a shielded
inductor for L1. The recommended shielded inductor is available from Coilcraft: MSS1278T-154. Please refer to:
http://www.coilcraft.com/pdfs/mss1278t.pdf.
Rev. 1.2
9
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